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AMD published October 11, 2026 a blog post explaining how its programmable AI NIC architecture supports Ultra Ethernet Consortium, Multipath Reliable Connection, and MetaRoCE transports for AI workloads.
AMD published a blog post on October 11, 2026 explaining how its AI NIC technology supports multiple Ethernet transport protocols developed for large-scale artificial intelligence workloads. The post, attributed to AMD Networking, describes the company’s programmable network interface card architecture as enabling organizations to adopt different congestion control and load balancing approaches without replacing hardware.
According to the AMD blog, the company cited a Gartner forecast projecting that more than 80% of hyperscalers will choose Ethernet for AI workloads by 2028. AMD stated that large-scale AI training requires fast recovery from congestion and path failures, packet spray load balancing, and source routing capabilities that traditional Ethernet transports such as RoCEv2 were not originally designed to provide.
Three Transport Protocols in Sixteen Months
AMD reported that three new AI-ready Ethernet transports emerged in a 16-month period, highlighting what the company described as the pace of AI networking innovation. The blog post detailed AMD’s involvement with each transport specification.
In 2025, the Ultra Ethernet Consortium—comprising more than 100 industry members according to AMD—developed an open Ethernet architecture for AI and high-performance computing environments. AMD stated it was a founding member and authored Network-Signaled Congestion Control, now included in the consortium’s congestion management specification. The company said it delivered one of the first AI NICs capable of supporting the UEC transport specification.
In 2026, Multipath Reliable Connection was initially developed by OpenAI with contributions from AMD, Microsoft, and other participants before being contributed to the Open Compute Project, according to AMD’s account. The company stated that MRC is deployed at Microsoft and Oracle to train OpenAI’s frontier models, and that AMD co-led authorship of the specification. AMD said its programmable AI NIC architecture provided a platform for implementation, testing, and validation.
Also in 2026, Meta developed MetaRoCE to support its AI training environments, AMD reported. The company stated that Meta worked directly with AMD to implement the transport on AMD AI NIC technology and validated MetaRoCE on 400G AMD AI NIC hardware.
Programmable Architecture and Hardware Generations
AMD emphasized that its AI NIC technology is “the only fully programmable AI NIC architecture available today,” allowing customers to implement new transport capabilities on existing hardware. The company stated that customers can develop and deploy transports on AMD Pensando Pollara 400 AI NICs and carry that work forward to AMD Pensando Vulcano 800 AI NICs.
Verified background context as of October 13, 2026 describes the Pensando Pollara 400 as supporting up to 400 Gbps Ethernet with a PCIe 5.0 x16 host interface and a programmable P4 processing engine. AMD’s July 23, 2026 description of Pensando Vulcano 800 specifies 800 Gbps connectivity per NIC and configurations with three NICs per GPU, providing up to 2.4 Tbps of aggregate scale-out bandwidth per GPU. These are AMD-published specifications, not independent performance verification.
As of October 13, 2026, AMD shares traded at $599.27 with a market capitalization of $994.57 billion. The company provided no specific deployment timelines, customer adoption metrics, or revenue projections related to AI NIC technology in the October 11 blog post.
Source: www.amd.com.
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Original reporting or announcement. Other cited links provide additional evidence; a source link alone does not establish independent verification.
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